Date posted 05/03/2026
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You see layout as engineering, not just drawing boxes. You catch latch-up and EMIR risks early and know how to fix them. You’re comfortable in Custom Compiler SDL or Virtuoso XL, and you close DRC, LVS, Antenna, and DFM issues without drama. You collaborate well with teams around the world, automate what you can, and write down what works so everyone benefits. When someone asks about ESD, you have answers, not just references.
What You'll Be Doing
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Creating and optimizing analog mixed signal layouts with a focus on device matching, EMIR awareness, and parasitic minimization using Custom Compiler SDL or Virtuoso XL
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Owning top-down macro floor planning and driving layout from concept to sign-off, coordinating with circuit designers and verification teams
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Running and resolving DRC, LVS, Antenna, DFM, and other physical verification checks, making layout choices that reduce rework later
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Performing PERC verification for ESD and latch-up, proactively identifying and fixing risks before tape out
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Use internal AI tools to reduce layout efforts and increase productivity
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Collaborating with layout teams in other geographies, sharing best practices, and keeping everyone moving in the same direction
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Documenting new methodologies and improvements in MS Word and PowerPoint, making sure the team can repeat and scale what works
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Automating layout and verification flows through scripting in partnership with the automation team, enabling engineers to spend more time solving problems and less time on repetitive tasks
What You'll Need
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Bachelor’s or Master’s degree in Electrical Engineering or Computer Science or other related field, with 5+ years of relevant experience.
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Demonstrated expertise in analog mixed signal layout, with hands-on experience in device and signal matching, EMIR, and parasitic optimization
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Proficiency with custom layout tools such as Custom Compiler SDL or Virtuoso XL
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Solid command of DRC, LVS, Antenna, DFM, and other physical verification processes
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Experience with PERC verification for ESD and latch-up; you know what to look for and how to fix it
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Ability to own and floorplan top-down macros, coordinating layout from high-level architecture to final sign-off
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Scripting skills in TCL, Perl, or Python to automate tasks and improve flows is a plus
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Experience creating clear methodology documentation using MS Word and PowerPoint is a plus
The Impact You Will Have
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Deliver layouts that pass verification the first time, cutting down on iteration cycles and speeding up tape out schedules for the whole team
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Raise the bar on device matching, EMIR, and parasitic performance, improving silicon yield and reliability for every project you touch
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Reduce post-layout surprises by building ESD and latch-up protection into the design, not after the fact
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Streamline global team workflows by sharing automation and documentation that actually gets used
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Push the quality of the overall design process, leaving a trail of improvements and higher standards for others to build on
Who You Are
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You anticipate layout risks and solve them before they become problems in silicon
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You collaborate with global teams and can get alignment even when everyone is remote
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You write down what works,
